FPGA implementation of Integer DCT for HEVC
نویسنده
چکیده
-In this paper, area-efficient architectures for the implementation of integer discrete cosine transform (DCT) of different lengths to be used in High Efficiency Video Coding (HEVC) are proposed. An efficient constant matrix multiplication scheme can be used to derive parallel architectures for 1-D integer DCT of different lengths such as 4, 8, 16, and 32. Also power-efficient structures for folded and full-parallel implementations of 2-D DCT is implemented with proposed architecture. The proposed architecture with 32-point length is 29.2% and 9.2% area efficient, also results in 13.1% and 2.8% less Area-Delay product respectively when compared to basic and existing models. Also pruning is applied to proposed architecture to improve the performance which results in 50.78% decrease in area Delay product for 32-point integer DCT. Key Words-High Efficiency Video Coding (HEVC), integer discrete cosine transform (DCT), video coding.
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